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A framework to generate domain-specific manycore architectures from dataflow programs
School of Information Technology, Halmstad University, Halmstad, Sweden; Department of Computers Science, Lund University, Lund, Sweden.
School of Information Technology, Halmstad University, Halmstad, Sweden.
Umeå universitet, Teknisk-naturvetenskapliga fakulteten, Institutionen för tillämpad fysik och elektronik.ORCID-id: /0000-0002-0562-2082
2020 (engelsk)Inngår i: Microprocessors and microsystems, ISSN 0141-9331, E-ISSN 1872-9436, Vol. 72, artikkel-id 102908Artikkel i tidsskrift (Fagfellevurdert) Published
Abstract [en]

In the last 15 years we have seen, as a response to power and thermal limits for current chip technologies, an explosion in the use of multiple and even many computer cores on a single chip. But now, to further improve performance and energy efficiency, when there are potentially hundreds of computing cores on a chip, we see a need for a specialization of individual cores and the development of heterogeneous manycore computer architectures.

However, developing such heterogeneous architectures is a significant challenge. Therefore, we propose a design method to generate domain specific manycore architectures based on RISC-V instruction set architecture and automate the main steps of this method with software tools. The design method allows generation of manycore architectures with different configurations including core augmentation through instruction extensions and custom accelerators. The method starts from developing applications in a high-level dataflow language and ends by generating synthesizable Verilog code and cycle accurate emulator for the generated architecture.

We evaluate the design method and the software tools by generating several architectures specialized for two different applications and measure their performance and hardware resource usages. Our results show that the design method can be used to generate specialized manycore architectures targeting applications from different domains. The specialized architectures show at least 3 to 4 times better performance than the general purpose counterparts. In certain cases, replacing general purpose components with specialized components saves hardware resources. Automating the method increases the speed of architecture development and facilitates the design space exploration of manycore architectures.

sted, utgiver, år, opplag, sider
Elsevier, 2020. Vol. 72, artikkel-id 102908
Emneord [en]
Domain-specific, Multicore, Manycore, Accelerator, Code generation, Hardware/software co-design, Riscv, Rocket core, Rocketchip, Cal2many
HSV kategori
Identifikatorer
URN: urn:nbn:se:umu:diva-165295DOI: 10.1016/j.micpro.2019.102908ISI: 000513294700002OAI: oai:DiVA.org:umu-165295DiVA, id: diva2:1371452
Forskningsfinansiär
Swedish Foundation for Strategic Research VinnovaTilgjengelig fra: 2019-11-20 Laget: 2019-11-20 Sist oppdatert: 2020-03-12bibliografisk kontrollert

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